This invention relates to the deposition of metal layers, such as the conductors in an integrated circuit.
In integrated circuits (ICs), metal layers are used to make electrical contact to device active areas (e.g., as electrodes to the gate, source and drain of FETs) and to interconnect devices to one another (e.g., as runners between devices on the same level of an IC or as vias between devices on different levels). In both cases, vias or windows with essentially vertical sidewalls are opened in an overlying dielectric layer to expose a portion of an underlying layer (e.g., the semiconductor active areas of devices or the commonly referred to "Metal-1" of the first level of metalization). A plug of metal from an overlying metal layer (e.g., "Metal-1" in the case of a device contacts or the commonly referred to "Metal-2" in the case of interconnects) extends through the via or window and makes an electrical connection between a metal layer and a semiconductor (device contact) or between two metal layers (interconnect). For simplicity, we will hereinafter refer to the electrical connection in both cases (metal to semiconductor, and metal to metal) as an interconnect.
Aluminum and aluminum alloys are the most common materials used for such metal layers. Typically, these Al-based layers are deposited as single layers by means of a single-step deposition such as sputtering. Al-based, single-layer metalization, however, suffers several major problems when used to form interconnects in vias or windows: (1) poor step coverage at a top edge of the window, (2) pinch-off or a lack of metal deposition along a sidewall of the window, and (3) overhang or excessive metal above a top edge of the window. Any one or more of these problems may adversely affect IC reliability. Thus, poor step coverage and overhang often produce voids (an absence of metal) in the windows which reduce the ability of the interconnect to carry current. Pinch-off, on the other hand, causes electron crowding, and hence undesirably high current densities, in the sidewall regions where metal is absent.
Lack of adequate step coverage in vertical or near vertical-walled openings or vias, especially those with aspect ratios greater than unity, is often addressed in the prior art by using tapered (i.e., sloped) sidewalls. However, this taper technology results in a larger pitch. Because a larger pitch means increased spacing between parallel metal conductors (e.g., runners), any significant taper is likely to render this technology unsuitable for design rules of, say, 0.5.mu.m, 0.3.mu.m or
Other prior art approaches to filling high aspect ratio vias entail multiple step metalization processes. In one case, a thick metal layer is deposited at a cold temperature, and the remainder of the metal is deposited as the temperature is ramped up to allow for reflow of the metal layer. See U.S. Pat. No. 4,970,176 granted to C. J. Tracy et al. on Nov. 13, 1990. In another case, a very thin layer of small grain aluminum is deposited at a cold temperature, typically below 350.degree. C. Deposition is stopped until the temperature is increased to the required deposition temperature, over 500.degree. C., and then deposition of aluminum is resumed. See U.S. Pat. No. 5,108,951 (col. 4, lines 1-9) granted to F. E. Chen et al. on Apr. 28, 1992. The Chen et al. patent goes on to describe an alternative technique in which aluminum is deposited continuously while the wafer is being heated. That is, a small amount of aluminum is deposited at or below 350.degree. C., and as the wafer gradually heats to the desired deposition temperature (400-500.degree. C.), aluminum deposition continues. Chen et al. reports that this technique gives a layer of aluminum which is deposited with very small grain sizes, tending to minimize grain size growth at later stages (col. 4, lines 10-21).
None of these multi-step metalization processes for filling high aspect ratio vias, however, recognizes the important relationship between interconnect performance and the need for a plug which has both a large grain size and a particular texture (i.e., grain orientation).
Thus, a need remains in the art for a metalization scheme that addresses the above problems in fabricating interconnects in essentially vertical-walled vias or windows. A particular need remains for such a metalization scheme which is suitable for high aspect ratio vias such as those present at sub-half-micron design rules.